High Dynamic Range Imaging with TDC-Based CMOS SPAD Arrays

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronou...

متن کامل

High Dynamic Range Imaging

High dynamic range (HDR) images and video contain pixels, which can represent much greater range of colors and brightness levels than that offered by existing, standard dynamic range images. Such “better pixels” greatly improve the overall quality of visual content, making it appear much more realistic and appealing to the audience. HDR is one of the key technologies of the future imaging pipel...

متن کامل

Column-Parallel Dynamic TDC Reallocation in SPAD Sensor Module Fabricated in 180nm CMOS for Near Infrared Optical Tomography

A major problem for optical biomedical imaging methods, e.g. near-infrared optical tomography (NIROT), using time resolved SPAD sensors is a slow acquisition time, resulting in motion artefacts and decreased patient comfort. We present a new SPAD sensor module optimised for the NIROT application. Dynamic TDC reallocation is employed to reduce the die area occupied by timing circuitry whilst als...

متن کامل

3um Pitch, 1um Active Diameter SPAD Arrays in 130nm CMOS Imaging Technology

A shared well 4x4 SPAD array test structure with 3m pitch is realized in a 130nm CMOS image sensor technology. The SPADs have 150Hz median DCR at room temperature at 1V excess bias, 15% peak PDP and 176ps FWHM timing jitter both at 3V excess bias.

متن کامل

3m Pitch, 1m Active Diameter SPAD Arrays in 130nm CMOS Imaging Technology

A shared well 4x4 SPAD array test structure with 3m pitch is realized in a 130nm CMOS image sensor technology. The SPADs have 150Hz median DCR at room temperature at 1V excess bias, 15% peak PDP and 176ps FWHM timing jitter both at 3V excess bias.

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Instruments

سال: 2019

ISSN: 2410-390X

DOI: 10.3390/instruments3030038